For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
The further reduction in scale of integrated circuit devices has called for the increased usage of non-planar transistors such as tri-gate transistors, FinFETs, TFETS, omega-FETs, and double-gate transistors. Among the non-planar transistors, Gate-All-Around transistors provide a better control of the channel by having a gate structure surrounding the channel on four surfaces. However, maintaining mobility improvements while increasing short channel control is still a major challenge. Many different techniques have been attempted to improve controlling source to drain leakage, however, significant improvements are still needed.